Design of an Integrated Circuit (IC) chip such as Application-Specific ICs (ASICs) and system-on-chips (SoC's) is a very complex, expensive, and time-consuming task. To help streamline this task, designers often utilize silicon IPs (also known as intellectual property blocks, IP cores, or integrated circuit macros) to facilitate the design task. IPs are units of reusable design whose use may have been licensed from a third party IP vendor. IPs may represent design components such as processor units, interface protocols, data storage elements, functions, etc. that may be utilized in the design of an ASIC or SoC. IPs commonly take the form of a digital, analog, or mixed signal IC described in a hardware description language (HDL) such as Verilog, VHDL, or System C but may also be represented as a netlist or physical layout. While using IP blocks in a design can provide significant efficiencies when compared with designing a chip at the transistor level or gate level, management of a large number of IP blocks has its own complexities.
As SoCs and other designs grow larger and more sophisticated, the task of integrating complex silicon IP blocks into a system becomes increasingly labor intensive and time consuming. To simplify the use and transfer of IPs, designers often utilize an Extensible Markup Language (XML) Schema such as those compliant with SPIRIT 1.0 XML to create an IP databook in XML to document features and configurability options and also package design data files for an IP. SoC design and stitching tools may use the standard XML Schema (such as the SPIRIT 1.0 XML Schema specification for IP design re-use promulgated by the SPIRIT Consortium) data to automate the painstaking IP integration process, leaving designers with more time to evaluate the performance of the IP block, its behavior and performance in context of the entire system, explore design alternatives, and focus engineering resources on design features that differentiate the end product. IP-based design tools include tools such as Mentor Graphics® Corporation's Platform Express™ for IP-based SoC stitch and design or Synopsys® Corporation's DesignWare® coreBuilder, coreConsultant, and coreAssembler, both of which support SPIRIT 1.0 XML compliant IP. Accordingly, IP that is packaged and delivered based on the Spirit XML Schema can be brought into these tools for processing. In addition, IPs packaged by Synopsys' coreBuilder can be used in other SPIRIT compliant tools.
While existing tools can accommodate schema compliant with the SPIRIT XML standard, these tools cannot easily handle schema that vary from this standard in structure and content. Schemas comporting to existing schema standards are effectively hardcoded into the architecture of these tools and the tools thus do not satisfactorily support variations or extensions of these schema. If, for example, an organization desired to use a schema that differed from the supported standards, their options would be limited. The organization could request from the SPIRIT consortium (or other standard bodies) to add the requested changes to the existing schema and, once approved, the design tool companies would need to update their system to accommodate the new schema, a process that may take years. In some cases, such a request may also be rejected, leaving the organization with the new schema with no ability to use existing design tools with their schema. There is, therefore, a need for an effective and efficient system to manage schemas for silicon IP that facilitates the use of different types of schemas, including those not part of an existing and supported standard. There is also a need for a flexible schema architecture for silicon IP design and delivery management.